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74ALVT16501
18-bit universal bus transceiver; 3-state
Rev. 04 -- 8 August 2005 Product data sheet
1. General description
The 74ALVT16501 is a high-performance Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) product designed for VCC operation at 2.5 V and 3.3 V with I/O compatibility up to 5 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).
2. Features
s s s s s s s s s s s s s 18-bit bidirectional bus interface 5 V I/O compatible 3-state buffers Output capability: +64 mA to -32 mA TTL and LVTTL input and output switching levels Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Positive-edge triggered clock inputs Latch-up protection: x JESD78: exceeds 500 mA ESD protection: x MIL STD 883, method 3015: exceeds 2000 V x Machine model: exceeds 400 V
Philips Semiconductors
74ALVT16501
18-bit universal bus transceiver; 3-state
3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C. Symbol Parameter VCC = 2.5 V tPLH tPHL Ci Cio ICC tPLH tPHL Ci Cio ICC propagation delay An to Bn or Bn to An propagation delay An to Bn or Bn to An input/output capacitance of I/O pins quiescent supply current propagation delay An to Bn or Bn to An propagation delay An to Bn or Bn to An input/output capacitance of I/O pins quiescent supply current CL = 30 pF CL = 30 pF 2.0 2.1 4 8 40 1.8 1.9 4 8 60 ns ns pF pF A ns ns pF pF A Conditions Min Typ Max Unit
input capacitance of control pins VI = 0 V or VCC VI/O = 0 V or VCC outputs disabled CL = 50 pF CL = 50 pF
VCC = 3.3 V
input capacitance of control pins VI = 0 V or VCC VI/O = 0 V or VCC outputs disabled
4. Ordering information
Table 2: Ordering information Package Temperature range Name 74ALVT16501DL -40 C to +85 C SSOP56 TSSOP56 Description plastic shrink small outline package; 56 leads; body width 7.5 mm plastic thin shrink small outline package; 56 leads; body width 6.1 mm Version SOT371-1 SOT364-1 Type number
74ALVT16501DGG -40 C to +85 C
74ALVT16501_4
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Product data sheet
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74ALVT16501
18-bit universal bus transceiver; 3-state
5. Functional diagram
1 OEAB 55 CPAB 2 LEAB 30 28 27 55 2 LEBA OEBA LEAB CPBA CPAB 1 OEAB 27 OEBA 30 CPBA 28 LEBA
54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26
EN1 2C3 C3 G2 EN4 5C6 C6 G5 3D 4 1 1 1 6D 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26
001aad339
001aad338
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74ALVT16501_4
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Product data sheet
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74ALVT16501
18-bit universal bus transceiver; 3-state
OEAB LEBA
1 28
CPBA
30
CPAB
55 2
LEAB
OEBA
27
C1 ID
C1 ID
1 of 18 channels A0 3 C1 ID C1 ID 54 B0
to 17 other channels
001aad340
Fig 3. Logic diagram
74ALVT16501_4
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Product data sheet
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74ALVT16501
18-bit universal bus transceiver; 3-state
6. Pinning information
6.1 Pinning
OEAB LEAB A0 GND A1 A2 VCC A3 A4
1 2 3 4 5 6 7 8 9
56 GND 55 CPAB 54 B0 53 GND 52 B1 51 B2 50 VCC 49 B3 48 B4 47 B5 46 GND 45 B6 44 B7 43 B8 42 B9 41 B10 40 B11 39 GND 38 B12 37 B13 36 B14 35 VCC 34 B15 33 B16 32 GND 31 B17 30 CPBA 29 GND
001aad337
A5 10 GND 11 A6 12 A7 13 A8 14 A9 15 A10 16 A11 17 GND 18 A12 19 A13 20 A14 21 VCC 22 A15 23 A16 24 GND 25 A17 26 OEBA 27 LEBA 28
16501
Fig 4. Pin configuration
6.2 Pin description
Table 3: Symbol OEAB LEAB A0 GND A1 A2 VCC A3
74ALVT16501_4
Pin description Pin 1 2 3 4 5 6 7 8 Description A-to-B output enable input A-to-B latch enable input data input or output (A side) ground (0 V) data input or output (A side) data input or output (A side) voltage supply data input or output (A side)
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Product data sheet
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74ALVT16501
18-bit universal bus transceiver; 3-state
Pin description ...continued Pin 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Description data input or output (A side) data input or output (A side) ground (0 V) data input or output (A side) data input or output (A side) data input or output (A side) data input or output (A side) data input or output (A side) data input or output (A side) ground (0 V) data input or output (A side) data input or output (A side) data input or output (A side) voltage supply data input or output (A side) data input or output (A side) ground (0 V) data input or output (A side) B-to-A output enable input (active LOW) B-to-A latch enable input ground (0 V) B-to-A clock input (active rising edge) data input or output (B side) ground (0 V) data input or output (B side) data input or output (B side) voltage supply data input or output (B side) data input or output (B side) data input or output (B side) ground (0 V) data input or output (B side) data input or output (B side) data input or output (B side) data input or output (B side) data input or output (B side) data input or output (B side) ground (0 V) data input or output (B side) data input or output (B side) data input or output (B side)
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table 3: Symbol A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 OEBA LEBA GND CPBA B17 GND B16 B15 VCC B14 B13 B12 GND B11 B10 B9 B8 B7 B6 GND B5 B4 B3
74ALVT16501_4
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Philips Semiconductors
74ALVT16501
18-bit universal bus transceiver; 3-state
Pin description ...continued Pin 50 51 52 53 54 55 56 Description voltage supply data input or output (B side) data input or output (B side) ground (0 V) data input or output (B side) A-to-B clock input (active rising edge) ground (0 V)
Table 3: Symbol VCC B2 B1 GND B0 CPAB GND
7. Functional description
7.1 Function table
Table 4: Function table [1] Control OEAB OEBA Disabled Disabled, latch data Disabled, hold data Disabled, clock data Transparent Latch data and display Clock data and display Hold data and display L L L L H H H H LEAB LEBA H L L H L L CPAB CPBA X X H or L X X H or L Input An Bn X h l X h l H L h l h l X X
[1] H = HIGH voltage level; h = HIGH voltage level one setup time prior to the enable or clock transition; L = LOW voltage level; I = LOW voltage level one setup time prior to the enable or clock transition; NC = no change; X = don't care; Z = high-impedance OFF-state; = HIGH-to-LOW enable or clock transition; = LOW-to-HIGH enable or clock transition.
Operating mode
Internal registers
Output Bn An Z Z Z Z Z Z H L H L H L H L
X H L NC H L H L H L H L H L
74ALVT16501_4
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Product data sheet
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74ALVT16501
18-bit universal bus transceiver; 3-state
8. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO IIK IOK IO Tstg Tj
[1] [2]
Conditions
[1]
Min -0.5 -0.5 -0.5 -65
[2]
Max +4.6 +7.0 +7.0 -50 -50 128 -64 +150 150
Unit V V V mA mA mA mA C C
supply voltage input voltage output voltage input diode current output diode current output current storage temperature junction temperature output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state output in HIGH-state
[1]
-
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability.
9. Recommended operating conditions
Table 6: Recommended operating conditions Conditions Min 2.3 0 1.7 none current duty cycle 50 %; f 1 kHz t/V Tamb VCC VI VIH VIL IOH input transition rise or fall rate ambient temperature supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current outputs enabled free air -40 3.0 0 2.0 Typ Max 2.7 5.5 0.7 -8 8 24 10 +85 3.6 5.5 0.8 -32 Unit V V V V mA mA mA ns/V C V V V V mA Symbol Parameter VCC = 2.5 V 0.2 V VCC VI VIH VIL IOH IOL supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current
VCC = 3.3 V 0.3 V
74ALVT16501_4
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74ALVT16501
18-bit universal bus transceiver; 3-state
Recommended operating conditions ...continued Conditions none current duty cycle 50 %; f 1 kHz Min -40 Typ Max 32 64 10 +85 Unit mA mA ns/V C LOW-level output current
Table 6: IOL
Symbol Parameter
t/V Tamb
input transition rise or fall rate ambient temperature
outputs enabled free air
10. Static characteristics
Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = -40 C to +85 C . Symbol Parameter VCC = 2.5 V 0.2 VIK VOH V [1] VCC = 2.3 V; IIK = -18 mA VCC = 2.3 V to 3.6 V; IOH = -100 A VCC = 2.3 V; IOH = -8 mA VOL LOW-level output voltage VCC = 2.3 V; IOL = 100 A VCC = 2.3 V; IOL = 24 mA VCC = 2.3 V; IOL = 8 mA VRST ILI power-up LOW-state output voltage input leakage current control pins I/O data pins IOFF IHOLD IEX IPU, IPD power-down leakage current bus hold current data inputs external current into output VCC = 2.7 V; VI = VCC or GND VCC = 0 V or 2.7 V; VI = 5.5 V VCC = 2.7 V; VI = VCC VCC = 2.7 V; VI = 0 V VCC = 0 V; VI or VO = 0 V to 4.5 V VCC = 2.3 V; VI = 0.7 V VCC = 2.3 V; VI = 1.7 V output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 2.3 V
[5] [4] [4] [3] [3]
Conditions
Min VCC - 0.2 1.8 [2]
Typ
Max
Unit V V V V V V V
input diode voltage HIGH-level output voltage
-0.85 -1.2 0.07 0.3 0.2 0.5 0.4 0.55
VCC = 2.7 V; IO = 1 mA; VI = VCC or GND
-
-
0.1 0.1 0.1 +0.1 0.1 90 -75 5 4
1 10 1 -5 100 125 100
A A A A A A A A A
power-up/down 3-state output current VCC 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OEAB or OEBA don't care quiescent supply current VCC = 2.7 V; VI = GND or VCC; IO = 0 A outputs HIGH-state outputs LOW-state outputs disabled
ICC
[6] [7]
0.04 2.5 0.04 0.01
0.1 4.5 0.1 0.4
mA mA mA mA
-
ICC
additional quiescent supply current per input pin input capacitance of control pins
VCC = 2.3 V to 2.7 V; one input at VCC - 0.6 V, other inputs at VCC or GND VI = 0 V or VCC
Ci
74ALVT16501_4
-
4
-
pF
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Product data sheet
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74ALVT16501
18-bit universal bus transceiver; 3-state
Table 7: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = -40 C to +85 C . Symbol Parameter Cio VIK VOH input/output capacitance of I/O pins V [8] VCC = 3.0 V; IIK = -18 mA VCC = 3.0 V to 3.6 V; IOH = -100 A VCC = 3.0 V; IOH = -32 mA VOL LOW-level output voltage VCC = 3.0 V; IOL = 100 A VCC = 3.0 V; IOL = 16 mA VCC = 3.0 V; IOL = 32 mA VCC = 3.0 V; IOL = 64 mA VRST ILI power-up LOW-state output voltage input leakage current control pins I/O data pins VCC = 3.6 V; VI = VCC or GND VCC = 0 V or 3.6 V; VI = 5.5 V VCC = 3.6 V; VI = 5.5 V VCC = 3.6 V; VI = VCC VCC = 3.6 V; VI = 0 V IOFF IHOLD power-down leakage current bus hold current data inputs VCC = 0 V; VI or VO = 0 V to 4.5 V VCC = 3 V; VI = 0.8 V VCC = 3 V; VI = 2.0 V VCC = 0 V to 3.6 V; VI = 3.6 V IEX IPU, IPD external current into output output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V
[10] [9] [9] [9] [3] [3] [3]
Conditions VI/O = 0 V or VCC
Min -
Typ 8
Max -
Unit pF V V V V V V V V
VCC = 3.3 V 0.3
input diode voltage HIGH-level output voltage
-0.85 -1.2 0.2 0.4 0.5 0.55 0.55
VCC - VCC 0.2 2.0 [2]
2.3 0.07 0.25 0.3 0.4 -
VCC = 3.6 V; IO = 1 mA; VI = VCC or GND
-
75 -75 500 -
0.1 0.1 0.1 0.5 +0.1 0.1 130 -140 10 1.0
1 10 20 10 -5 100 125 100
A A A A A A A A A A A
power-up/down 3-state output current VCC 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OEAB or OEBA don't care quiescent supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH-state outputs LOW-state outputs disabled
ICC
[6] [7]
0.06 3.5 0.06 0.04
0.1 5 0.1 0.4
mA mA mA mA
-
ICC
additional quiescent supply current per input pin input capacitance of control pins input/output capacitance of I/O pins
VCC = 3 V to 3.6 V; one input at VCC - 0.6 V, other inputs at VCC or GND VI = 0 V or VCC VI/O = 0 V or VCC
Ci Cio
[1] [2] [3] [4] [5]
-
4 8
-
pF pF
All typical values are at VCC = 2.5 V and Tamb = 25 C. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. Unused pins at VCC or GND. Not guaranteed. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V 0.2 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only.
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74ALVT16501_4
Product data sheet
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Philips Semiconductors
74ALVT16501
18-bit universal bus transceiver; 3-state
[6] [7] [8] [9]
ICC is measured with outputs pulled up to VCC or pulled down to ground. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. All typical values are at VCC = 3.3 V and Tamb = 25 C. This is the bus hold overdrive current required to force the input to the opposite logic state.
[10] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only.
11. Dynamic characteristics
Table 8: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Tamb = -40 C to +85 C. Symbol Parameter VCC = 2.5 V 0.2 V [1]; CL = 30 pF tPLH propagation delay An to Bn or Bn to An LEAB to Bn or LEBA to An CPAB to Bn or CPBA to An tPHL propagation delay An to Bn or Bn to An LEAB to Bn or LEBA to An CPAB to Bn or CPBA to An tPZH tPZL tPHZ tPLZ th(H) output enable time to HIGH-level output enable time to LOW-level output disable time from HIGH-level output disable time from LOW-level hold time HIGH An to CPAB or Bn to CPBA An to LEAB or Bn to LEAB th(L) hold time LOW An to CPAB or Bn to CPBA An to LEAB or Bn to LEAB tsu(H) set-up time HIGH An to CPAB or Bn to CPBA An to LEAB or Bn to LEBA tsu(L) set-up time LOW An to CPAB or Bn to CPBA An to LEAB or Bn to LEBA tWH pulse width HIGH CPAB or CPBA LEAB or LEBA tWL fmax
74ALVT16501_4
Conditions
Min
Typ
Max
Unit
see Figure 5 see Figure 6 see Figure 7 see Figure 5 see Figure 6 see Figure 7 see Figure 9 see Figure 10 see Figure 9 see Figure 10 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 7 see Figure 6 see Figure 7 see Figure 7
1.0 1.5 2.2 1.4 1.5 1.9 2.3 1.9 2.2 1.6 0 +1.0 +1.0 2.0 1.9 0 2.5 +1.0 3.0 1.5 3.0 150
2.0 2.4 3.6 2.1 2.3 3.2 3.9 3.3 3.4 2.8 -1.2 -0.5 -0.4 1.0 0.4 -1.0 1.2 -0.5 -
3.0 4.0 5.4 3.5 4.0 5.4 5.0 4.4 4.4 3.4 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
pulse width LOW CPAB or CPBA maximum clock frequency
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Product data sheet
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74ALVT16501
18-bit universal bus transceiver; 3-state
Table 8: Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Tamb = -40 C to +85 C. Symbol Parameter VCC = 3.3 V 0.3 tPLH V [2]; CL = 50 pF see Figure 5 see Figure 6 see Figure 7 see Figure 5 see Figure 6 see Figure 7 see Figure 9 see Figure 10 see Figure 9 see Figure 10 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 7 see Figure 6 see Figure 7 see Figure 7 1.2 1.5 2.1 1.1 1.4 1.7 2.2 1.6 2.7 2.1 +1.0 1.0 +1.0 1.5 2.0 +1.0 2.0 +1.0 2.0 1.5 2.0 150 1.8 2.4 3.0 1.9 2.1 2.6 3.3 2.5 3.6 3.0 -0.6 0.1 -0.3 0.6 0.5 -0.6 0.7 -0.1 2.9 3.5 4.3 2.8 3.6 4.1 4.5 3.6 4.9 4.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz propagation delay An to Bn or Bn to An LEAB to Bn or LEBA to An CPAB to Bn or CPBA to An tPHL propagation delay An to Bn or Bn to An LEAB to Bn or LEBA to An CPAB to Bn or CPBA to An tPZH tPZL tPHZ tPLZ th(H) output enable time to HIGH-level output enable time to LOW-level output disable time from HIGH-level output disable time from LOW-level hold time HIGH An to CPAB or Bn to CPBA An to LEAB or Bn to LEAB th(L) hold time LOW An to CPAB or Bn to CPBA An to LEAB or Bn to LEAB tsu(H) set-up time HIGH An to CPAB or Bn to CPBA An to LEAB or Bn to LEBA tsu(L) set-up time LOW An to CPAB or Bn to CPBA An to LEAB or Bn to LEBA tWH pulse width HIGH CPAB or CPBA LEAB or LEBA tWL fmax
[1] [2]
Conditions
Min
Typ
Max
Unit
pulse width LOW CPAB or CPBA maximum clock frequency
All typical values are measured at VCC = 2.5 V and Tamb = 25 C. All typical values are measured at VCC = 3.3 V and Tamb = 25 C.
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74ALVT16501
18-bit universal bus transceiver; 3-state
12. Waveforms
VI input An or Bn 0V t PLH VOH output Bn or An VOL
001aad308
VM
VM
t PHL
VM
VM
Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load.
Fig 5. Propagation delay input (An, Bn) to output (Bn, An) in transparent mode
VI input LEAB or LEBA 0V t WH t PHL VOH output An or Bn VOL
001aad310
VM
VM
VM
t PLH
VM
VM
Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load.
Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable (LEAB, LEBA) pulse width
1/f max VI input CPBA or CPAB 0V t WH t PHL VOH output An or Bn VOL VM VM
001aad254
VM
VM
VM
t WL t PLH
Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load.
Fig 7. Propagation delay clock (CPAB, CPBA) to output (An, Bn), clock (CPAB, CPBA) pulse width and maximum clock frequency (CPAB, CPBA)
74ALVT16501_4
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74ALVT16501
18-bit universal bus transceiver; 3-state
LEAB or LEBA input
VI VM VM
CPAB or CPBA 0 V t su(H) VI input An, Bn 0V
001aad342
t h(H)
t su(L)
t h(L)
VM
VM
VM
VM
Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 8. Data setup and hold times
OEBA input OEAB
VI VM 0V t PZH VOH t PHZ VY VM
output An or Bn 0V
VM
001aad344
Measurement points are given in Table 9. VOH is typical voltage output drop that occur with the output load.
Fig 9. 3-state output enable time to HIGH-level and output disable time from HIGH-level
OEBA input OEAB
VI VM 0V t PZL 3.0 V or VCC t PLZ VM
output An or Bn VOL
VM
VX
001aad346
Measurement points are given in Table 9. VOL is typical voltage output drop that occur with the output load.
Fig 10. 3-state output enable time to LOW-level and output disable time from LOW-level
74ALVT16501_4
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74ALVT16501
18-bit universal bus transceiver; 3-state
Measurement points Input VM 1.5 V 0.5 x VCC Output VM 1.5 V 0.5 x VCC VX VOL + 0.30 V VOL + 0.15 V VY VOH - 0.30 V VOH - 0.15 V
Table 9:
Supply voltage 3.0 V 2.7 V
VI negative pulse 0V
tW 90 % VM 10 % tTHL(tf) tTLH(tr) tTLH(tr) tTHL(tf) VM 90 %
VI positive pulse 0V 10 %
90 % VM tW
001aac221
VM 10 %
Measurement points are given in Table 9.
a. Input pulse definition
VEXT VCC PULSE GENERATOR VI DUT
RT CL RL RL
VO
mna616
Test data is given in Table 10. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times.
b. Test circuit Fig 11. Load circuitry for switching times Table 10: Input VI 3.0 V or VCC whichever is less fi tW tr, tf 10 MHz 500 ns Test data Load CL RL 2.5 ns 30 pF or 500 50 pF VEXT tPLZ, tPZL tPLH, tPHL tPHZ, tPZH 6 V or 2 x open VCC GND
74ALVT16501_4
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18-bit universal bus transceiver; 3-state
13. Package outline
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1
D
E
A X
c y HE vM A
Z 56 29
Q A2 A1 (A 3) Lp 1 bp 28 wM L detail X A
pin 1 index
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 18.55 18.30 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-18
Fig 12. Package outline SOT371-1 (SSOP56)
74ALVT16501_4 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 -- 8 August 2005
16 of 20
Philips Semiconductors
74ALVT16501
18-bit universal bus transceiver; 3-state
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
D
E
A
X
c y HE vMA
Z
56
29
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp wM
28
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 14.1 13.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.5 0.1 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 13. Package outline SOT364-1 (TSSOP56)
74ALVT16501_4 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 -- 8 August 2005
17 of 20
Philips Semiconductors
74ALVT16501
18-bit universal bus transceiver; 3-state
14. Revision history
Table 11: Revision history Release date 20050808 Data sheet status Product data sheet Change notice Doc. number Supersedes 74ALVT16501_3 Document ID 74ALVT16501_4 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Section 2 "Features": modified `JEDEC Std. 17' into `JESD78'. Table 8 "Dynamic characteristics": changed maximum values of propagation delay, output enable time and output disable time. Product specification 9397 750 03567 74ALVT16501_2 74ALVT16501_1 -
74ALVT16501_3 74ALVT16501_2 74ALVT16501_1
19980213 -
74ALVT16501_4
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 -- 8 August 2005
18 of 20
Philips Semiconductors
74ALVT16501
18-bit universal bus transceiver; 3-state
15. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74ALVT16501_4
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 -- 8 August 2005
19 of 20
Philips Semiconductors
74ALVT16501
18-bit universal bus transceiver; 3-state
20. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 8 August 2005 Document number: 74ALVT16501_4
Published in The Netherlands

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